A NAND type flash memory, which is a nonvolatile semiconductor memory device, is widely used as a mass data storage device. Currently, it is expected that further miniaturization will progress as the reduction in cost per bit and the increase in capacity progress by the miniaturization of memory elements. However, for further miniaturization of a flash memory, there are many problems to solve, such as development of lithography technology and suppression of short channel effects, inter-element interference and inter-element variation. For this reason, there is a high possibility that it becomes difficult to further improve the storage density continuously only by the development of miniaturization technology in a simple plane.
Therefore, in recent years, in order to increase the integration density of memory cells, development for transition from a conventional two-dimensional (planar) memory structure to a three-dimensional (volumetric) memory structure has been made, and a variety of three-dimensional nonvolatile semiconductor memory devices have been proposed. Among them, a vertical gate (VG) type semiconductor memory structure is characterized in that a stacked active area (AA) and a gate contact (GC) can be formed collectively since a layout including peripheral elements is substantially equal to a planar structure.
However, when a NAND type memory cell array structure is employed, a memory string includes a memory cell and a select transistor. Also, usually, unlike a memory cell having a floating gate electrode (FG), a select transistor is formed in a metal-insulator-semiconductor (MIS) type not having a floating gate electrode (FG) so that a threshold value thereof does not vary.
In order to realize such a select transistor, in the conventional technology, while a select transistor and a memory cell have the same structure, a portion corresponding to a floating gate electrode (FG) and a portion corresponding to a control gate electrode (CG) in the select transistor are shorted mutually by employing a process of providing a hole in an inter-electrode insulating layer. Accordingly, a MIS type select transistor can be realized.
However, it is very difficult to employ this technology in a vertical gate type semiconductor memory structure. This is because, in such a three-dimensional structure, a floating gate electrode and a control gate electrode are aligned in a direction parallel to the surface of a semiconductor substrate. Therefore, in such a three-dimensional nonvolatile semiconductor memory device, when a MIS type select transistor not having a floating gate electrode is formed forcibly, the characteristic degradation and failure of a select transistor occur due to misalignment or the like.